DSPIC30F6013T-20I/PF【PDF 43/228 页】IC DSPIC MCU/DSP 132K 80TQFP

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Sheet目录3879

39页 40页 41页 42页 [43页]44页 45页 46页 47页

2006 Microchip Technology Inc.

DS70117F-page 135

dsPIC30F6011/6012/6013/6014

19.0

12-BIT ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The 12-bit Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 12-bit digital

number. This module is based on a Successive

Approximation Register (SAR) architecture and pro-

vides a maximum sampling rate of 200 ksps. The ADC

module has up to 16 analog inputs which are multi-

plexed into a sample and hold amplifier. The output of

the sample and hold is the input into the converter

which generates the result. The analog reference volt-

age is software selectable to either the device supply

voltage (AVDD/AVSS) or the voltage level on the

(VREF+/VREF-) pin. The ADC has a unique feature of

being able to operate while the device is in Sleep mode

with RC oscillator selection.

The ADC module has six 16-bit registers:

ADC Control Register 1 (ADCON1)

ADC Control Register 2 (ADCON2)

ADC Control Register 3 (ADCON3)

ADC Input Select Register (ADCHS)

ADC Port Configuration Register (ADPCFG)

ADC Input Scan Selection Register (ADCSSL)

The ADCON1, ADCON2 and ADCON3 registers con-

trol the operation of the A/D module. The ADCHS reg-

ister selects the input channels to be converted. The

ADPCFG register configures the port pins as analog

inputs or as digital I/O. The ADCSSL register selects

inputs for scanning.

The block diagram of the 12-bit ADC module is shown

in Figure 19-1.

FIGURE 19-1:

12-BIT ADC FUNCTIONAL BLOCK DIAGRAM

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

Note:

The SSRC<2:0>, ASAM, SMPI<3:0>,

BUFM and ALTS bits, as well as the

ADCON3 and ADCSSL registers, must

not be written to while ADON = 1. This

would lead to indeterminate results.

Comparator

12-bit SAR

Conversion Logic

VREF+

DAC

Dat

16-word, 12-bit

Dual Port

RAM

Inte

AN12

0000

0101

0111

1001

1101

1110

1111

1100

0001

0010

0011

0100

0110

1000

1010

1011

AN13

AN14

AN15

AN8

AN9

AN10

AN11

AN4

AN5

AN6

AN7

AN0

AN1

AN2

AN3

CH0

AN1

VREF-

Sample/Sequence

Control

Sample

Input MUX

Control

Input

Switches

S/H

AVSS

AVDD

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